1. Field
The present description relates to electrical interconnections for semiconductors and micromachines, and, in particular, to compliant interconnects between a die and a package that can be formed using photolithography technology.
2. Background
In a typical IC package, a semiconductor wafer is fabricated using processes like photolithography, etching, chemical vapor deposition and acid washing. The wafer is cut into individual dies or chips. Each die is attached to a substrate that is then mounted onto a printed circuit board. A cover is attached to the substrate to cover, seal and protect the die. The die has electrical interconnects to the substrate, and the substrate provides connections to a socket or a main printed circuit board. The substrate has a much larger surface than the die, so larger and simpler connectors, such as wire pins, solder balls, and coils may be used. For the connection between the die and the substrate, however, these conventional larger interconnections limit how small and complex a die may become.
Rapid advances in IC (Integrated Circuit) design and fabrication continue to challenge and push electronic packaging technology in size, performance, cost, and reliability. One aspect of these advances is the decreasing amount of space available on an IC to connect the IC to the external environment for power and data communications. As more and more connections are forced into a smaller space, the conventional wire pins, solder balls and other large structures will no longer fit on the outside surface of the IC. In addition, wire pins and solder balls do not provide the reliability, performance, cost, and ease of manufacture needed for high volume IC manufacturing in these size ranges.
As an example, solder bumps, such as C4 (Controlled-Collapse Chip Connection) bumps, are being increasingly used for microelectronics packaging. Solder bumps allow for smaller chip size, more input and output connectors and shorter connection paths. However, because of the large difference in coefficients of thermal expansion between the chip and the substrate to which the chip is connected, an underfill material is often applied surrounding the solder bumps. The underfill reduces the shear strain in the solder bump caused by the different rates of expansion and contraction as the chip heats and cools. Unfortunately, the underfill adds a step to the manufacturing process and prevents the components from being disconnected for rework.
To eliminate the complex, and tedious underfill and solder reflow processes and to allow for interconnections that are even smaller and closer together, compliant interconnects have been proposed that can be fabricated using conventional photolithography and electroplating technologies. By integrating the fabrication of the interconnects with the fabrication of the rest of the chip's wafer-level processing, the cost of making the interconnects can be kept low.
Interconnect structures and other structures can be made in a variety of different ways. One proposed technology is with conventional photoresist layering, developing and etching techniques. In conventional photoresist processing, the photoresist is applied in a solid layer, exposed to light in a two-dimensional pattern, and then either the exposed or unexposed portion is etched off, leaving the two-dimensional pattern with a thickness equal to the original photoresist layer.
In order to add a third dimension to the shape, solvents have been used to reflow the photoresist into curved forms. The solvents are diffused over the photoresist in a constant pressure partial vacuum and at a constant temperature. However, even at constant temperature and pressure, the shape of the photoresist structure is difficult to control and the solvent acts inconsistently. The resulting structures are uneven and irregular. When elongated half cylinders are made the structures vary in height and width along their length.